Riyansh K. Karani, Akash K. Rana, Dhruv H. Reshamwala and Kishore Saldanha, Dwarkadas J. Sanghvi College of Engineering, India

Floating point division, even though being an infrequent operation in the traditional sense, is indis-pensable when it comes to a range of non-traditional applications such as K-Means Clustering and QR Decomposition just to name a few. In such applications, hardware support for floating point division would boost the performance of the entire system. In this paper, we present a novel architecture for a floating point division unit based on the Taylor-series expansion algorithm. We show that the Iterative Logarithmic Multiplier is very well suited to be used as a part of this architecture. We propose an implementation of the powering unit that can calculate an odd power and an even power of a number simultaneously, meanwhile having little hardware overhead when compared to the Iterative Logarithmic Multiplier.

Floating point division, Iterative Logarithmic Multiplier, Taylor-series