P. Koti Lakshmi and Rameshwar Rao, Osmania University, India

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.

Low PDP design, High speed OR gate, Domino OR gate, Low power design.